CPRI

Product Details

• CPRI multi-hop Remote Radio Head Reference Design
• Ask Xilinx About this Core

Documentation

• CPRI
• Release Notes (PDF)
• Xilinx Core Site License (PDF)

Device Family Support

• Virtex-6 -1L
• Virtex-6 CXT
• Virtex-6 LXT
• Virtex-6 SXT
• Virtex-5 FXT
• Virtex-5 LXT
• Virtex-5 SXT
• Spartan-6 LXT

The LogiCORE™ CPRI IP core is a high-performance IP solution that implements the Common Packet Radio Interface (CPRI). The IP core uses state-of-the-art RocketIO™ GTP/GTX transceivers to implement the CPRI Physical Layer and provides a compact and customizable Data Link Layer implemented in the FPGA fabric. The CPRI core is ideal for connectivity between Radio Equipment Controllers (REC) or baseband/channel cards and one or more Radio Equipment units (radio cards). It provides an optimized implementation supporting radio I/Q data, radio unit management, and synchronization in a single efficient protocol.

Key Features

• Designed to CPRI Specification v4.1
• Operates at line rates of 614.4 Mbps, 1228.8 Mbps, 2457.6 Mbps, 3.072 Mbps using Xilinx GTP transceivers
• Operates at line rates of 614.4, 1228.8, 2457.6, 3072, 4915.2, and 6144 Mbps using Xilinx GTXE1 transceivers
• Automatic speed negotiation
• Configurable as master or slave
• Suitable for use in both Radio Equipment, Controllers (RECs) and Radio Equipment (RE), including multi-hop systems
• Supports 1 to 24 Antenna-Carriers per core
• Available through the Xilinx CORE Generator™