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Memory Interfaces with Xilinx FPGAs
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Memory Interface Design with MIG 3.3
Create faster, less expensive, and lower power memory interfaces with Xilinx Virtex-6 and Spartan-6 FPGAs

Memory Solutions

Xilinx memory interface solutions are based on hardware-verified reference designs and software tools that enable you to quickly generate your own custom design.

View Video: Create faster, less expensive, and lower power memory interfaces with Xilinx Virtex-6 and Spartan-6 FPGAs

Simplify memory device selection and controller implementation with the following application notes, reference designs and the Memory Interface Generator (MIG).

Memory Interface Support for FPGAs
Memory Type Virtex-6 Spartan-6 Virtex-5 Virtex-4 Extended
Spartan-3A
DDR3 SDRAM 1066 Mbps† 800 Mbps† 800 Mbps** - -
533 MHz 400 MHz 400 MHz
DDR2 SDRAM 800 Mbps† 800 Mbps† 667 Mbps 600 Mbps 400 Mbps*
400 MHz 400 MHz 333 MHz 300 MHz 200 MHz
DDR SDRAM 400 Mbps† 400 Mbps† 400 Mbps 344 Mbps 333 Mbps
200 MHz 200 MHz 200 MHz 172 MHz 166 MHz
LPDDR SDRAM - 400 Mbps† - - -
200 MHz
QDR II/QDRII+ SRAM 2 x 800 Mbps† - 2 x 600 Mbps 2 x 550 Mbps -
400 MHz 300 MHz 275 MHz
RLDRAM II 1000 Mbps† - 667Mbps 470 Mbps -
500 MHz 333 MHz 235 MHz

Notes:

*Spartan®-3A/AN devices support 400 Mbps DDR2 interfaces (see Application Note: XAPP458).
**Virtex®-5 800 Mbps DDR3 subject to characterization.
†Virtex-6 and Spartan-6 support is subject to characterization.

Additional Memory Resources by FPGA

Virtex-6 FPGAs

Spartan-6 FPGAs

Virtex-5 FPGAs

Spartan-3 Generation FPGAs

DDR2 reference design and DDR2-400 video demo for the Spartan-3A Starter Kit board. Registered users may download complete files.
First time users | Registered users

DDR reference design for the Spartan-3E Starter Kit. Registered users may download complete files.
First time users | Registered users

Memory Interface Generator (MIG)

Generate your Virtex-6, Spartan-6, Virtex-5, Virtex-4, and Spartan-3 generation memory interface reference designs, including HDL code and pin placements, using this user-friendly tool.

First time users | Registered users

Registered users may download the User Guide and the MIG tool. The User Guide contains information such as recommended pin constraints, PCB trace matching, termination schemes, clock-capable IO rules, bank recommendations, DCI, and ODT suggestions.
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