Wireless Communications
Publications
Xilinx offers high-performance, cost-effective solutions for wireless networking equipment, in areas such as RF digital front end (DFE) signal processing, baseband processing (including forward error correction (FEC), Fourier transforms and adaptive modulation), and advanced interfacing, connectivity and bridging solutions. Xilinx and our partners offer:
- Reference designs and hardware platforms to simplify the development of high-performance radio and baseband processing functions.
- Flexible and upgradeable solutions that meet the challenges of evolving standards, such as WCDMA, WiMAX, TD-SCDMA and LTE.
- IP and reference designs to support the latest radio, baseband and DSP connectivity standards, such as CPRI, OBSAI and SRIO.
- Industry leading FEC solutions, such as advanced Turbo Codec algorithms, which improve throughput, reduce latency and lower cost-per-channel.
- A comprehensive portfolio of networking solutions to support the development of new, low-latency, base station architectures and the transition towards an All-IP core and backhaul network.
Our available resources, organized by function and type, include:
Leverage the capabilities of our newest Virtex®-5 FPGA for your demanding wireless solutions.
Wireless communications resources are also available for:
Accelerate LTE Basestation Design and Development
| Interfaces and Connectivity | |||
|---|---|---|---|
| Topic | Resource | Type | Provider |
| OBSAI RP3 | OBSAI RP3/RP3-01 v4.0 IP Core Device architecture: Virtex-5 LXT/SXT |
IP | Xilinx, Inc. |
| CPRI | CPRI v2.1 IP Core Device architecture: Virtex-5 LXT/SXT |
IP | Xilinx, Inc. |
| CPRI Multi-hop | CPRI Multi-hop Remote Radio Head Reference Design | IP | Xilinx, Inc. |
| JEDEC JESD204A | JEDEC JESD204A FPGA Receive Reference Design | IP | Xilinx, Inc. |
| SRIO | SRIO | Custom search | Xilinx, Inc. |
| PCI Express® | Development Kit for PCI Express | Development kit | Xilinx, Inc. |
| Ethernet MAC | Ethernet MAC built-in hard IP for Virtex-5 LXT/SXT FPGA | Silicon feature | Xilinx, Inc. |
| EMIF | XAPP753 - FPGA Interface to the TMSC6000 DSP Platform Using EMIF (PDF) | App note | Xilinx, Inc. |
| LinkPort | XAPP634 - Analog Devices TigerSHARC Link (PDF) | App note | Xilinx, Inc. |
| XAPP635 - Interfacing Virtex-II Series FPGAs With Analog Devices TigerSHARC TS20x DSPs via LVDS Link Ports (PDF) | App note | Xilinx, Inc. | |
| High Speed ADC/DAC Interface | ADC/DAC application notes | Custom search | Xilinx, Inc. |
| RF (Radio Card) | |||
|---|---|---|---|
| Topic | Resource | Type | Provider |
| Peak Cancellation Crest Factor Reduction (PC-CFR) | Peak Cancellation Crest Factor Reduction |
IP Core | Xilinx, Inc. |
| Digital Pre-Distortion (DPD) | Digital Pre-distortion V3.0 IP Core Product Brief |
IP Core | Xilinx, Inc. |
| LTE | LTE Digital Front End Reference Design (login required) Supports latest 3GPP-LTE standard Optimized design with small footprint Device architecture: Virtex-5 FPGA Channel Bandwidths – 5, 10, 15, 20MHz ACLR ≥ 60 dB CFR: 1 carrier (EVM≤2% at 8dB PAPR) |
Reference design | Xilinx, Inc. |
| WCDMA/HSPA | WCDMA/HSPA Reference Design (login required) Device architecture: Virtex-4, Virtex-5 FPGA DUC: 3 carrier DDC: 6 carrier (receiver diversity) CFR: 3 carrier (PAPR<6 dB@<11% EVM, >60 dB ACLR) |
Reference design | Xilinx, Inc. |
| WiMAX | WiMAX Reference Design (login required) Device architecture: Virtex-4, Virtex-5 FPGA DUC: 1 carrier (dynamic switching 3.5, 5, 7 and 10 MHz) DDC: 1 carrier (dynamic switching 3.5, 5, 7 and 10 MHz) CFR: 1 carrier (PAPR>1.5 dB@2% EVM) |
Reference design | Xilinx, Inc. |
| WiMAX Reference Design (login required) Device architecture: Spartan®-3A DSP FPGA DUC: 1 carrier (dynamic switching 5 and 10 MHz) DDC: 1 carrier (dynamic switching 5 and 10 MHz) |
Reference design | Xilinx, Inc. | |
| TD-SCDMA | TD-SCDMA Reference Design (login required) Device architecture: Virtex-4 FPGA DUC: up to 6 carrier DDC: up to 6 carrier |
Reference design | Xilinx, Inc. |
| DUC/DDC | Modulation and demodulation IP Device architecture: various |
Custom search | Xilinx, Inc. and partners |
| XAPP1018 - Designing Efficient DUC/DDC with System Generator and Core Generator (PDF) | App note | Xilinx, Inc. | |
| XAPP1113 - Designing Efficient Digital Up and Down Converters for Narrowband Systems (inc. Multi-Carrier GSM example) (PDF) Device Architecture: Virtex-5 DUC and DDC for 4-carrier GSM |
App note | Xilinx, Inc. | |
| Baseband Processing (Channel Card) | |||
|---|---|---|---|
| Topic | Resource | Type | Provider |
| LTE | LTE Baseband TDP Downlink Tx Reference Design v1 (Implements all downlink layer1 channels specified by the 3GPP-LTE specifications. PPC440 based EDK project targeting V5FX70T / ML507. Source code design instantiating the following LogiCOREs: LTE Turbo Encoder v2, LTE MIMO Encoder v1 and FFT v5. Documented in XAPP1115). |
Reference design | Xilinx, Inc. |
| LTE Baseband TDP Downlink Rx Reference Design v1 (Simple UE emulator, PPC440 based EDK project targeting V5FX70T / ML507. source code instantiates the following LogiCOREs: LTE Turbo Decoder v1, FFT v5. Documented in XAPP1116). |
Reference design | Xilinx, Inc. | |
| LTE Baseband TDP System Reference Design v1 (PPC440 based EDK project targeting V5FX70T / ML507. Source code integrates LTE Baseband TDP Downlink Tx and Downlink Rx Reference Designs listed above. Documented in XAPP1120) |
Reference design | Xilinx, Inc. | |
| LTE MIMO Encoder LogiCORE | IP | Xilinx, Inc. | |
| LTE MIMO Decoder LogiCORE | IP | Xilinx, Inc. | |
| LTE Channel Encoder LogiCORE | IP | Xilinx, Inc. | |
| LTE Channel Decoder LogiCORE | IP | Xilinx, Inc. | |
| LTE Turbo Encoder LogiCORE | IP | Xilinx, Inc. | |
| LTE Turbo Decoder LogiCORE | IP | Xilinx, Inc. | |
| WCDMA/HSPA | Downlink Chip Rate LogiCORE | IP | Xilinx, Inc. |
| RACH Preamble Detector LogiCORE | IP | Xilinx, Inc. | |
| Searcher LogiCORE | IP | Xilinx, Inc. | |
| TCC Encoder | IP | Xilinx, Inc. | |
| TCC Decoder | IP | Xilinx, Inc. | |
| WiMAX | WiMAX IEEE802.16-2004 FEC Reference Design (login required) System Generator 8.1 and later Tx and Rx chains including Randomiser/Derandomizer, RS/Viterbi FEC encode/decode, Interleaver/Deinterleaver, QAM Mapper/Demapper |
Reference design |
Xilinx, Inc. |
| CTC Encoder | IP | Xilinx, Inc. | |
| CTC Decoder | IP | Xilinx, Inc. | |
| LDPC Encoder | IP | Xilinx, Inc. | |
| Generic | Discrete Fourier Transform (DFT) | IP | Xilinx, Inc. |
| Fast Fourier Transform (FFT) | IP | Xilinx, Inc. | |
| Reed-Solomon IP | Custom search | Xilinx, Inc. | |
| Viterbi/Convolutional IP | Custom search | Xilinx, Inc. | |